REGISTER TRANSFER LEVEL DESIGN OF LOGIC GATES USING VERILOG
AND GATE:
//AND Gate Verilog Digital Design > Priyavrat Bhardwaj .v file//
module and_gate (
a, //first_input
b, //second_input
y //output
);
//input logic:
input a, b;
//output logic:
output y;
//code:
assign y = a & b;
endmodule;
//AND Gate Testbench Verilog Digital Design tb.v file//
module andgate_tb;
reg A, B;
wire Y;
and_gate a1 ( .a(A), .b(B), .y(Y)); //connecting by names
initial
begin
$monitor(A, B, Y);
$monitor(A, B, Y);
A = 1'b0;
B = 1'b0;
#5
A = 1'b0;
B = 1'b1;
#5
A = 1'b1;
B = 1'b0;
#5
A = 1'b1;
B = 1'b1;
end
endmodule
 |
| Waveform: AND Gate logic; Run length = 10ns |
OR GATE:
//OR Gate Verilog Digital Design > Priyavrat Bhardwaj .v file//
module or_gate (
a, //first_input
b, //second_input
y //output
);
//input logic:
input a, b;
//output logic:
output y;
//code:
assign y = a | b;
endmodule;
//OR Gate Testbench Verilog Digital Design tb.v file//
module orgate_tb;
reg A, B;
wire Y;
or_gate a2 ( .a(A), .b(B), .y(Y)); //connecting by names
initial
begin
$monitor(A, B, Y);
A = 1'b0;
B = 1'b0;
#5
A = 1'b0;
B = 1'b1;
#5
A = 1'b1;
B = 1'b0;
#5
A = 1'b1;
B = 1'b1;
end
endmodule
 |
| Waveform: OR Gate logic; Runtime = 10ns |
NOR GATE:
//NOR Gate Verilog Digital Design > Priyavrat Bhardwaj .v file
module nor_gate (
a, //first_input
b, //second_input
y //output
);
//input logic:
input a, b;
//output logic:
output y;
//code:
assign y = a |~ b;
endmodule;
//NOR Gate Testbench Verilog Digital Design tb.v file//
module norgate_tb;
reg A, B;
wire Y;
nor_gate a2 ( .a(A), .b(B), .y(Y)); //connecting by names
initial
begin
$monitor(A, B, Y);
A = 1'b0;
B = 1'b0;
#5
A = 1'b0;
B = 1'b1;
#5
A = 1'b1;
B = 1'b0;
#5
A = 1'b1;
B = 1'b1;
end
endmodule
 |
| Waveform: NOR Gate logic; Runtime = 10ns |
NAND GATE:
//NAND Gate Verilog Digital Design > Priyavrat Bhardwaj .v file//
module nand_gate (
a, //first_input
b, //second_input
y //output
);
//input logic:
input a, b;
//output logic:
output y;
//code:
assign y = a &~ b;
endmodule;
//NAND Gate Testbench Verilog Digital Design tb.v file//
module nandgate_tb;
reg A, B;
wire Y;
nand_gate a3 ( .a(A), .b(B), .y(Y)); //connecting by names
initial
begin
$monitor(A, B, Y);
A = 1'b0;
B = 1'b0;
#5
A = 1'b0;
B = 1'b1;
#5
A = 1'b1;
B = 1'b0;
#5
A = 1'b1;
B = 1'b1;
end
endmodule
 |
| Waveform: NAND Gate logic; Runtime = 10ns |
XOR GATE:
//XOR Gate Verilog Digital Design > Priyavrat Bhardwaj .v file//
module xor_gate (
a, //first_input
b, //second_input
y //output
);
//input logic:
input a, b;
//output logic:
output y;
//code:
assign y = a ^ b;
endmodule;
//XOR Gate Testbench Verilog Digital Design tb.v file//
module xorgate_tb;
reg A, B;
wire Y;
xor_gate a2 ( .a(A), .b(B), .y(Y)); //connecting by names
initial
begin
$monitor(A, B, Y);
A = 1'b0;
B = 1'b0;
#5
A = 1'b0;
B = 1'b1;
#5
A = 1'b1;
B = 1'b0;
#5
A = 1'b1;
B = 1'b1;
end
endmodule
 |
| Waveform: XOR Gate logic; Runtime = 10ns |
XNOR GATE:
//XNOR Gate Verilog Digital Design > Priyavrat Bhardwaj .v file//
module xnor_gate (
a, //first_input
b, //second_input
y //output
);
//input logic:
input a, b;
//output logic:
output y;
//code:
assign y = a ^~ b;
endmodule;
//XNOR Gate Testbench Verilog Digital Design tb.v file//
module xnorgate_tb;
reg A, B;
wire Y;
xnor_gate a2 ( .a(A), .b(B), .y(Y)); //connecting by names
initial
begin
$monitor(A, B, Y);
A = 1'b0;
B = 1'b0;
#5
A = 1'b0;
B = 1'b1;
#5
A = 1'b1;
B = 1'b0;
#5
A = 1'b1;
B = 1'b1;
end
endmodule
 |
| Waveform: XNOR Gate Logic; Runtime = 10ns |
NOT GATE:
//NOT Gate Verilog Digital Design > Priyavrat Bhardwaj .v file//
module not_gate (
x, //input
y //output
);
//input logic:
input x;
//output logic:
output y;
//code:
assign y = ~x;
endmodule;
//NOT Gate Testbench Verilog Digital Design tb.v file//
module notgate_tb;
reg X;
wire Y;
not_gate a2 ( .x(X), .y(Y)); //connecting by names
initial
begin
$monitor(X, Y);
#0
X = 1'b0;
#5
X = 1'b1;
end
endmodule
 |
| Waveform: NOT Gate logic; Runtime = 10ns |
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