System Verilog (Part A) - Design Aspects

FUNDAMENTALS OF DIGITAL IC DESIGN:

• In digital circuits, the real world data is converted to binary data (1 and 0) using mathematical formulas. 1 can be represented as Positive Voltage, and 0 can be represented as Negative or Ground Voltage.
• Types of Digital Circuits:
• Sequential - Output value depends on the present value as well as on the past input value of the circuit, "with memory".
• Combinational - Output value depends only on the present input value, "without memory".
• Building blocks of Digital Circuits are:
• Logic Gates - AND, OR, NOT, XOR, XNOR, NAND, NOR
• Flip-Flops - The memory cells.
• All logic gates and flip-flops are built using only Transistors.

IC MANUFACTURING CYCLE:

• Architecture Specification: 
• Idea
• Unit, Block and System level
• Digital Design (RTL) and Verification (Front End)
• Physical Design (Circuit/Layout) and Verification (Back End)
• Gate level netlist
• Physical Implementation
• GDSII
• Ready to go to plants (Tape out)
• IC manufacturing (manufacturing cycles), packing and final testing
• Product release: Chip

VERILOG:

• Developed by Gateway Design in 1984 which was acquired by Cadence Design Systems in 1989.
• Verilog HDL is now maintained by a non-profit organization called Accellera.
• Language Reference Manual (LRM): The IEEE Verilog standard document - 1364.
• Revision: 1995, 2001 and 2005.
• Enumeration is not available.
• No OOP support.

SYSTEM VERILOG:

• Developed by Accellera as an extension of Verilog: IEEE 1800 standard in 2005.
• Has enhanced verification capabilities, supporting OOP for verification.
• Enumeration available.

FIRST SYSTEM VERILOG PROGRAM: ADDER

Fig: 8-Bit Full Adder

module adder (a,b,c_in,c_out,sum);
input [7:0] a;
input [7:0] b;
input [7:0] c_in; //> PORT DECLARATION
output [7:0] c_out;
output [7:0] sum;

logic [8:0] result;  //> INTERNAL SIGNALS

assign result=a+b+c_in;
assign sum=result[7:0];  //> FUNCTIONALITY
assign c_out=result[8];

endmodule: adder

In this program, 'result' has been declared as an internal variable which has been assigned 9 bits i.e. [8:0].

* To write a RTL design code, the code has to be written in a synthesizable manner.