Combinational Circuit Design using verilog with Testbenches

• MULTIPLEXER: A combinational logic circuit which selects a particular binary input line and directs it to the output line. //MUX
• Reduces number of wires, complexity, and cost.

CODE:

module mux( q, d, s );
input[1:0] s;
input[3:0] d;
output q;

wire q;
wire[1:0] s;
wire[3:0] d;

assign q = d[s];
endmodule

module mux_tb;
 reg[1:0] s;
reg[3:0] d;
wire q;

integer i;

mux four_mux( select, d, q );

initial
begin
#1 $monitor();

for( i = 0; i <= 15; i = i + 1)
begin
d = i;
select = 0; #1;
select = 1; #1;
select = 2; #1;
select = 3; #1;
$display("----------------");
end

end
endmodule

• FULL ADDER: It includes inputs A and B, carry in Cin, and Outputs S for sum; carry out Cout. Cout is only TRUE if any two of the three inputs are HIGH.

Fig: Full adder Gate level Schematic.

CODE:

module full_adder(s,ci,a,b,c);

  input a,b,ci;

  output s,c;

  wire s1,s2,s3;

  xor x1(s1,a,b);

  xor x2(s,s1,ci);

  and a2(s3,a,b);

  and a1(s2,s1,ci);

  or o1(c,s2,s3); 

//wire s1,s2,s3;

endmodule