Design and Test Bench in System Verilog

Posted by SemiSaga on
HDL based Design and Test Bench
  • Design: Synthesizable code
    • HDLs used for synthesis: Verilog, System Verilog or, VHDL
    • For synthesis, we cannot use all the language constructs of Verilog, System Verilog or, VHDL and it is restricted.
    • Once the HDL program is written, it is converted into actual hardware - which is a complex, costly and time-consuming process. Thus, any bug or issue is unacceptable.
  • Test Bench (TB) - It is used to 'test' or 'verify' the Design.
    • This can be in any programming language like C, C++, Verilog etc
    • Most widely acceptable TB language is 'System Verilog'
    • SV support a lot of in-depth verification features, like subject-oriented programming
    • Primary function of a TB is to inject stimulus to design and check for its correctness - verify.
    • For every design that you simulate, you have to write a simple testbench at least.
  • A Programmer in HDL should do both:
    • Write the synthesizable RTL code
    • Write a TB to verify the design
----------------------
A SIMPLE ADDER CIRCUIT
----FILE 1: Design----

//Design code

module adder # (parameter DATA_WIDTH=8) (input logic [DATA_WIDTH -1:0] a,b, input logic c_in, output logic [DATA_WIDTH-1:0] sum, output logic c_out);

logic [DATA_WIDTH:0] temp;

always_comb temp = a+b+c_in;
always_comb sum = temp [DATA_WIDTH-1:0];
always_comb c_out = temp [DATA_WIDTH];
endmodule: adder

----FILE 2: Verify----

`timescale 1ns/1ns
//Testbench Code

module test_bench ();
logic [15:0] a,b,s;
logic c_in,c_out;

adder # (.DATA_WIDTH(16)) adder_1 (.sum(s), .*);
      //adder # (.DATA_WIDTH(16)) adder_2 (.a(a), .b(b), .sum(s), .c_in(c_in), .c_out(c_out));

initial begin
//Dump waves
$dumpfile("dump.vcd");
$dumpvars(1, test_bench);

#10;
a='d10;
b=16'd15;
c_in=0;

#10;
a='d22;
b='d78;

#10;
a=16'hFFFF;
b=16'hFFFF;

#10;
c_in=0;

end

endmodule: test_bench

----------------------
COMBINATIONAL CIRCUIT
----FILE 3: Design----

//ALU Design Code
module alu # (parameter DATA_WIDTH = 8) (input logic [DATA_WIDTH -1:0] a,b, input logic [2:0] opcode, output logic [DATA_WIDTH-1:0] out);

always_comb begin
case (opcode)
'd0: begin out = a+b; end //Addition
'd1: begin out = a-b; end //Subtraction
'd2: begin out = a*b; end //Multiplication
'd3: begin out = a/b; end //Division
'd4: begin out = a&&b; end //Logical AND
'd5: begin out = a||b; end //Logical OR
'd6: begin out = a&b; end //Bitwise AND
'd7: begin out = a|b; end //Bitwise OR
endcase
end

endmodule: alu

----FILE 4: Verify----

`timescale 1ns/1ns
//TB
module test__bench ();

logic [3:0] d1,d2,x;
logic [2:0] opcode;

alu #(.DATA_WIDTH(4)) alu1 (.a(d1),.b(d2),.out(x), .*);

initial begin

//Dump waves
$dumpfile("dump.vcd");
$dumpvars(1, test__bench);

d1 = 5;
d2 = 2;
opcode = 0; //sum

#10
opcode=1;
#10 opcode=2;
#10 opcode=3;
#10 opcode=4;
#10 opcode=5;
#10 opcode=6;
#10 opcode=7;

#10 d1=3; d2=4; opcode=0;
end

endmodule: test__bench

------------------------------------------
SEQUENTIAL CIRCUIT DESIGN AND VERIFICATION
----FILE 5: Counter Design Code-----------

//Design code

module counter #(parameter WIDTH=4) (input logic clk, input logic reset, input logic up_dwbar, output logic [WIDTH-1:0] count);

always @(posedge clk) begin

if (reset) begin
count=0;
end else if (up_dwbar) begin
count=count+1;
end else if (up_dwbar==0) begin
count=count+1;
end

end
endmodule: counter

----FILE 6: Verify----

`timescale 1ns/1ns
//TB Counter

module counter_tb();
logic clk,rst,upcounter;
logic [7:0] count;

counter #(.WIDTH(8)) counter_1(.reset(rst),.up_dwbar(upcounter), .*);

//Clock Generator
always begin
#10 clk=~clk;
end

initial begin
//Dump waves
$dumpfile("dump.vcd");
$dumpvars(1, counter_tb);

//clk=0; //Initialize clk to 0 to avoid X propagation
//rst=0;

//@(posedge clk);
//rst=1;
//@(posedge clk);
//rst=0;

upcounter=1;
repeat (20) @ (posedge clk);
upcounter=0;
repeat (12) @ (posedge clk);
upcounter=1;
end

//always @(posedge clk) begin
//end

endmodule: counter_tb

Physical Design and Verification - Back End Process:
FIG: GDSII Stream format view of an example file

  • Design coding Verilog/ System Verilog / VHDL
  • Functional Verification of the design using Simulation. (System Verilog is used here)
  • Synthesis and Gate level netlist.
  • Circuit / Layout Design, Place and Route
  • GDS and GDS-II
    • GDS II files are usually the final output product of the IC design cycle and are given to IC foundries for fabrication.
    • Tapeout
  • Physical Verification, FPGA emulation
  • ECO - Engineering Change Order
  • Editing gate level netlist ECO.

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