Slave AXI-Stream Specification:
- Receives AXI-Stream Master provided data: When user is ready to get data from AXI Slave (or when user wants to enable AXIS module), it enables the ready to high.
- AXI-Stream Master sends data through AXI-Stream.
- When user application is ready to accept, enables ready input - can be only pulse signal.
- AXIS Slave receives that data and puts on data output.
- Enables finish signal after receiving the data, to notify user.
- AXI Stream ports are marked in a different color.
Design module of Slave AXI-Stream (.v file):
module axis_slave(
input areset_neg, aclk, //data that axis slave will receive
output reg [31:0] data, //user app is ready to accept data, so slave can receive a data
input ready,
output reg tready,
input tvalid, tlast,
input [31:0] tdata,
output reg finish //transaction is complete
);
//handshake happenend bw master and slave
wire handshake;
assign handshake = tvalid & tready;
//tready
always @(posedge aclk)
if (~areset_neg)
tready <= 1'b0;
else
if (ready && ~tready) //first time ready comes
tready <= 1'b1;
else
if (handshake) //handshake happened, ready goes low
tready <= 1'b0;
else
if (tready && ~ready && ~tvalid) //keep tready high, when user disables ready
tready <= 1'b1;
else
tready <= tready; //keep the value of tready
//data
always @(posedge aclk)
if (~areset_neg)
data <= 1'b0;
else if (handshake)
data <= tdata;
else
data <= data;
always @(posedge aclk)
if (~areset_neg)
finish <= 0;
else if (handshake)
finish <= 1'b1;
else
if (finish == 1 && ready)
finish <= 0;
else
finish <= finish;
endmodule
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| FIG: RTL Synthesis - top level. |
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| FIG: Elaborated RTL Design of AXIS Slave |
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