AXI-Lite Simulation

Simulation:

• We will connect our designed AXI-Lite Master to AXI-Lite Slave Verification IP.
• Exchange the data between them.
• This Verification IP acts as both Master and Slave.

FIG (ports): AXI Verification IP (Pass-Through).

FIG: AXI VIP Slave

• The AXI Verification IP can be either: MASTER, PASS THROUGH (it connect AXI Slave to Master), or SLAVE.
• This Protocol is supported by AXI3, AXI4, and AXI4LITE (choose this in Customize IP).
• Modes: Read Only, Read Write, Write Only.
• AXI VIP Slave
• Structure: The AXI VIP Can be configured in three different modes.
• AXI master VIP
• AXI slave VIP
• AXI pass-through VIP
• SystemVerilog Interface is used to communicate with external Testbench.
• Protocol related things are generated using AXI Protocol Checker.

AXI Slave VIP:

Test Bench for AXI Slave VIP

• Slave Agent: Agent of our Verification IP.
• TB is considered Static to a Virtual Interface.
• Interface: It is a SystemVerilog (SV) statement.
• It is an object which contains the module ports.

AXI Slave Agent:

AXI Slave VIP Agent Structure

• The Agent consists of three main parts:
• Write Driver: writes to AXI-Lite.
• Read Driver: Supports the Read part of AXI-Lite.
• Monitor: Control, check, and generate ready protocol transactions.
• Virtual Interface: Connect static and dynamic worlds.

*Please refer to the document for details.

Simple SRAM Memory Model:

FIG: Memory Model

• The AXI-Lite can contain memory in it. The AXI Slave VIP has a simple memory model and it is an associative array of SystemVerilog.
• The write transaction can write to the memory model and the read transaction can read data from the memory.
• At the same time, the memory model has backdoor APIs for you to access memory directly, which are:
• backdoor_memory_write: writes data to memory
• backdoor_memory_read: reads data from memory

VIP Usage Guideline:

• While coding the test bench for the AXI VIP, the following requirements must be met. Else, the AXI does not work. Also, these are the requirements for all VIPs.
• Create a module test bench as all other standard SystemVerilog test benches.

       module testbench();

       ...                

       endmodule          

• Import two required packages. axi_vip_pkg and <component_name>_pkg.
• The <component_name>_pkg includes agent classes and its subclasses for AXI VIP.
• Declare agents. One agent for one AXI VIP has to be declared.

Depending on the AXI VIP interface mode, different typedef class should be called for a declaration of the agent.

Name	Description
<component_name>_mst_t	Master VIP
<component_name>_slv_t	Slave VIP without memory model
<component_name>_slv_mem_t	Slave VIP with memory model
<component_name>_passthrough_t	Pass-through VIP without memory model
<component_name>_passthrough_mem_t	Pass-through VIP with memory model

• Create a new for the agent and pass the hierarchy path of IF correctly into the new function.

           agent = new("my VIP agent",<hierarchy_path>.IF);

Starting the VIP:

• For the VIP to start running, the start agent has to be called. The following shows how the slave VIPs start to run.
• AXI Slave VIP

        slv_agent.start_slave();

Example design is shown below:

AXI Master VIP

AXI Pass-Through VIP

AXI Slave VIP

Simulated Waveform Output.

Applications: The AXI VIP is for verification and system engineers who want to

• Monitor transactions between two AXI connections. 
• Generate AXI transactions. 
• Check for AXI protocol compliance.

AXI VIP Quiz:

Q1. For what purpose Verification IP can be used?

a. Monitor transactions between AXI connections.

b. Generate AXI Transactions.

c. Check for AXI protocol compliance

d. Synthesize the block in our system.

e. All of the above.

Q2. How to connect VIP to our DUT?

a. Using Interface construct.

b. Direct connection.

Q3. What is backdoor access?

a. Allows easily write to VIP memory, without AXI interface.

b. Mechanism to run VIP simulation.

XILINX: The AXI Verification IP can only act as a protocol checker when contained within a VHDL hierarchy. In order to use the virtual part of the AXI Verification IP, it must be in Verilog hierarchy. In order to use the virtual part of this IP, Please refer PG267 section (Click here to view the document) about "Useful Coding Guidelines and Examples "

Click Here to view this section on Xilinx website.