STRUCTURE & DATA TYPES:
- VHDL Keywords:
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library IEEE; --denotes specific library you are going to be using. Different libraries have different packages and these packages give you different functionality for functions, data types, and different operations (logical operations, math operations, etc).
If you are a C programmer or an embedded type of programmer, this^ could be compared to a 'header' file (or a .h type of file).
use IEEE.STD_LOGIC; --"use" is used to make a package from the library available to this design unit (define library > make the package available for use from the library)
entity example is --An entity in VHDL defines your inputs and outputs of your design. So, if you think of VHDL as a 'shell', then external is your entity, and the internal would be the keyword 'architecture'.
generic( -- this is the way you can pass certain parameters into your design (without actually defining input or output). For e.g. - if you are having an 8-bit adder or a 16-bit adder or a 32-bit adder you can have a generic, you call the size of an adder & give it that number (you don't have to define it as an input or an output). In short, it defines general parts of the design).
);
port ( --Defines the interface, I/O's of the design
My_input : in std_logic;
My_output : out std_logic_vector(31 downto 0)
);
);
--'downto' is used to define a range. Defines the middle of a range.
end example
architecture test of example --what's going on inside your design
begin
map
--map is used to map multiple parameters. So, if you have multiple designs inside one VHDL, i.e. port map in component instantiations. This is where you will map certain parameters. For e.g. inputs from my top-level entity are mapped to different inputs of the components I have instantiated inside my design.
map
--map is used to map multiple parameters. So, if you have multiple designs inside one VHDL, i.e. port map in component instantiations. This is where you will map certain parameters. For e.g. inputs from my top-level entity are mapped to different inputs of the components I have instantiated inside my design.
--Put your architecture code/design here
--begin & end pair defines the beginning and end of the
architecture.
--begin end pair is also used in if-else statements.
--begin & end pair defines the beginning and end of the
architecture.
--begin end pair is also used in if-else statements.
My_input <= My_Output(1);
A <= B;
--Signal Assignment "<=" is used to assign one signal to another inside a design.
end test;
*Design configuration and setting-up the Project / creating a New VHDL Project varies with each simulator (e.g. - Quartus-II OR Xilinx Vivado, both will have different steps to configure or create a new project).
A <= B;
--Signal Assignment "<=" is used to assign one signal to another inside a design.
*Design configuration and setting-up the Project / creating a New VHDL Project varies with each simulator (e.g. - Quartus-II OR Xilinx Vivado, both will have different steps to configure or create a new project).
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