Skip to main content

SemiSaga.com

Technology Blog

Search This Blog

Home
About
Bus / Protocol
UVM
SystemVerilog
CMOS VLSI
Digital System Design
Electronics and Programming
Videos
FPGA
Electrical Engineering
RF Design

Showing posts from January, 2020

Posts

A Powerful and Secondary Review: ASIC Design concepts

Posted by SemiSaga on January 12, 2020

Get link
Facebook
X
Pinterest
Email
Other Apps

Archive

September 20244
August 20244
July 20241
April 20241
February 20241
November 20221
May 20221
November 20201
August 20201
July 20201

May 20202
April 20201
March 20201
February 20202
January 20201
December 20192
November 201910
October 20199
September 20198
July 20192
June 20193
May 20191
April 20191
February 20192
January 20192
December 20181
November 20185

Show more Show less

Labels

Automation
bitcoin
blockchain
cmos
crypto
Electronics
fabrication
IT
mining
processors

Python
vlsi

Show more Show less

Report Abuse

Popular Posts

PCIe - TLP Header, Packet Formats, Address Translation, Config Space, Command Register, Configuration types

TLP Packet Format: FIG: TLP Packet Format. The Transaction Layer Packet Format is defined as: Starts with a Prefix, which is an optional one and, TLP Header and then, With/Without Data Payload, At the end of TLP Packet a TLP Digest, The information in TLP Packet Format is distributed as: TLP Prefixes. Header (mandatory). Data (included when applicable): depends on the transaction type. TLP Digest (optional). FIG: TLP Byte Information TLP Header: Provides Format of the packet. Type of the packet. Length of associated data, if available. Transaction Descriptor. Address/Routing information Byte enables Message encoding Completion Status FIG: Common TLP Header. 32-bit if information. Provides: Format, TLP Packet Type, Traffic Class info, Attributes, T Heads (Presence of TLP Prefix, if present), TLP Digest, End Point (TLP is Normal or Poisoned), Address Translation (When memory is available). Length (Data Length notation denoted in 32bit words) F...

System Verilog: Multiplexer

Fig: Multiplexer Multiplexer in digital circuit design is a circuit which selects one of its input by using the SELECT line. select[1:0] q 00 d[0] 01 d[1] 10 d[2] 11 d[3] FIG: 4 X 1 MUX. (Not Completely labeled); q1, q2, q3, q4 are the 4 outputs; a stands for and gate; o stands for or gate; n stands for not gate. SV Code (Gate-level model): module mux_gate_level( select, d, q ); input logic [1:0] select; input logic [3:0] d; output logic q; wire q1, q2, q3, q4; wire [1:0] SelectBar; not n1( SelectBar[0], select[0] ); not n2( SelectBar[1], select[1] ); and a1( q1, SelectBar[0], SelectBar[1], d[0] ); and a2( q2, select[0] , SelectBar[1], d[1] ); and a3( q3, SelectBar[0], select[1] , d[2] ); and a4( q4, select[0] , select[1] , d[3] ); or o1( q, q1, q2, q3, q4 ); endmodule SV C...

PCI Configuration Space Registers (Type 0 / Type 1)

PCI Configuration Space Type 0 is for PCI devices and, for Endpoints in case of PCIe. Type 1 Config Space is for PCI host controller and, for PCI Root Complex in case of PCIe. Type 0/1 Configuration Space: FIG: Config Space. The Config Space registers are common for both type 0/1. Device ID and Vendor ID: Identify the particular device. Status register: Provides error information, updated information, etc. Command register: Controls Bus Master and different utilities. Class code: Provides category of the device (Host Controller, IDE Bridge, SATA Controller, Ethernet Controller, etc). Revision ID of PCI. BIST - Built-In Self Test. Header Type Specific area is defined by Header type (0 or 1). Cache Line Size. Table: Configuration Space Registers. Table: Command Register Table: Status Register FIG: Type 0 Configuration Space Table: TYPE 0 Registers FIG: PCIe TYPE 1 Configuration Space Table: TYPE 1 Configuration Space Registers

Powered by Blogger